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W9725G6KB
30. Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock jitter spec
parameters'. The jitter specified is a random jitter meeting a Gaussian distribution.
Input clock-Jitter specifications parameters for DDR2-667, DDR2-800 and DDR2-1066
PARAMETER
SYMBOL
DDR2-667
MIN. MAX.
DDR2-800
MIN. MAX.
DDR2-1066
MIN. MAX.
UNIT
Clock period jitter
Clock period jitter during DLL locking period
Cycle to cycle clock period
Cycle to cycle clock period jitter during DLL
tJIT(per)
tJIT(per,lck)
tJIT(cc)
tJIT(cc,lck)
-125
-100
-250
-200
125
100
250
200
-100
-80
-200
-160
100
80
200
160
-90
-80
-180
-160
90
80
180
160
pS
pS
pS
pS
locking period
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across n cycles,
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6-10per)
-175
-225
-250
-250
-350
175
225
250
250
350
-150
-175
-200
-200
-300
150
175
200
200
300
-132
-157
-175
-188
-250
132
157
175
188
250
pS
pS
pS
pS
pS
n = 6 ... 10, inclusive
Cumulative error across n cycles,
tERR(11-50per)
-450
450
-450
450
-425
425
pS
n = 11 ... 50, inclusive
Duty cycle jitter
tJIT(duty)
-125
125
-100
100
-75
75
pS
Definitions:
tCK ( avg ) = ? ? tCK j ? / N
-
tCK(avg)
tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window.
? N ?
? j ? 1 ?
where
N = 200
tCH ( avg ) = ? ? tCH j ? / ( N × tCK ( avg ))
-
tCH(avg) and tCL(avg)
tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses.
? N ?
? j ? 1 ?
where
N = 200
tCL ( avg ) = ? ? tCL j ? / ( N × tCK ( avg ))
tCL(avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses.
? N ?
? j ? 1 ?
where
N = 200
Publication Release Date: Sep. 03, 2012
- 51 -
Revision A03
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